* Clock frequency: 166,143,100 MHz
* Fully synchronous; all signals referenced to a positive clock edge
* Internal bank for hiding row access/precharge
* .

A0-A11 A0-A9 BA0, BA1 I/O0 to I/O7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM VDD Vss VDDQ VssQ N.

42S16100

42S18160

42S32200

42S4210

42SL90QD

42SL90QD-AA

42-DL212

42-DL212B

42-DL214

42-DL221

420

42050

42051