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International Rectifier Electronic Components Datasheet

IP2003 Datasheet

MULTIPHASE OPTIMIZED LGA POWER BLOCK

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PD- 96922A
iP2003
Synchronous Buck
Multiphase Optimized LGA Power Block
Features:
Integrated Power Semiconductors, Drivers & Passives
• Full function multiphase building block
• Output current 40A continuous with no derating up to
TPCB = 100°C and TCASE = 100°C
• Operating frequency up to 1.0 MHz
• Efficient dual sided cooling
• Small footprint low profile (11mm x 11mm x 2.2mm) package
• Optimized for very low power losses
• LGA interface
• Ease of design
• Proprietary packaging enables ultra low Rthj-case top
Description
iP2003 Power Block
The iP2003 is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM IC, the
external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
iP2003 Internal Block Diagram
P RDY
ENABLE
PWM
VDD
SGND
MOSFET
Driver with
dead time
cont ro l
www.irf.com
VIN
VSW
P GND
Pin #
1
2
3
4
5, 7
11/18/04
6
8
Pin Name Pin Function
VDD Supply voltage for the internal circuitry.
When set to logic level high, internal circuitry
of the device is enabled. When set to logic
ENABLE level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current is less than 10µA.
PWM TTL-level input signal to MOSFET drivers.
PRDY
Power Ready - This pin indicates the status of
ENABLE or VDD. This output will be driven
low when ENABLE is logic low or when VDD
is less than 4.4V (typ.). When ENABLE is
logic high and VDD is greater than 4.4V (typ.),
this output is driven high. This output has a
10mA source and 1mA sink capability.
PGND
VSW
VIN
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
Input voltage for the DC-DC converter.
1


International Rectifier Electronic Components Datasheet

IP2003 Datasheet

MULTIPHASE OPTIMIZED LGA POWER BLOCK

No Preview Available !

iP2003
All specifications @25°C (unless otherwise specified)
Absolute Maximum Ratings:
Parameter
Symbol
VIN to PGND
VDD to PGND
VIN
VDD
PWM to PGND
PWM
Enable to PGND
ENABLE
Output RMS Current
IOUT
Block Temperature
TBLK
Min
-
-
-0.3
-0.3
-
-40
Typ Max Units
Conditions
- 16 V
- 6.0 V
- VDD +0.3 V Not to exceed 6.0V
- VDD +0.3 V Not to exceed 6.0V
- 40 A Measured at VSW
-
125
°C
Capable of start up over full
temperature range
Recommended Operating Conditions:
Parameter
Symbol Min Typ Max Units
Supply Voltage
VDD
4.6 5.0 5.5
V
Input Voltage
VIN 3.0 - 13.2 V
Output Voltage
VOUT 0.8 - 3.3 V
Output Current
IOUT - - 40 A
Operating Frequency
fsw 300 - 1000 kHz
Operating Duty Cycle
D - - 85 %
Conditions
Electrical Specifications @ VDD = 5V (unless otherwise specified):
Parameter
Symbol Min Typ Max Units
Block Power Loss c
PLOSS
-
9.4 11.7
W
Turn On Delay d
Turn Off Delay d
td(on)
td(off)
-
-
63
26
-
-
ns
VIN Quiescent Current
IQ-VIN - - 1.0 mA
VDD Quiescent Current
IQ-VDD - 10 - µA
Under-Voltage Lockout
UVLO
Start Threshold
VSTART 4.2 4.4 4.5
V
Hysteresis
VHvs-UVLO
-
150
-
mV
Enable
ENABLE
Input Voltage High
VIH 2.0 - - V
Input Voltage Low
VIL - - 0.8
Power Ready
PRDY
Logic Level High
VOH 4.5 4.6 -
V
Logic Level Low
VOL - 0.1 0.2
PWM Input
PWM
Logic Level High
VOH 2.0 - - V
Logic Level Low
VOL - - 0.8
Conditions
VIN=12V, VOUT=1.3V
IOUT=40A, fSW=1MHz
L = 0.3µH
Enable = 0V, VIN=12V
Enable = 0V, VDD=5V
VDD=4.6V, ILoad=10mA
VDD <UVLO Threshold, ILoad = 1mA
 Measurement were made using four 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
Fig. 8).
‚ Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
2 www.irf.com


Part Number IP2003
Description MULTIPHASE OPTIMIZED LGA POWER BLOCK
Maker International Rectifier
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IP2003 Datasheet PDF






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