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MR44V064A Datasheet Preview

MR44V064A Datasheet

FeRAM

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FEDR44V064A-02
Issue Date: Sep. 1, 2017
MR44V064A
64k Bit(8,192-Word × 8-Bit) FeRAM (Ferroelectric Random Access Memory) I2C
GENERAL DESCRIPTION
The MR44V064A is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. The MR44V064A is accessed using Two-wire
Serial Interface ( I2C BUS ).Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup
required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks,
such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and
the power consumption during a write can be reduced significantly.
The MR44V064A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 8,192-word × 8-bit configuration I2C BUS Interface
• A single 3.3 V typ (2.5V to 3.6V) power supply
• Operating frequency:
3.4MHz(Max) HS-mode
• Read/write tolerance
400KHz(Max) F/S-mode
1012 cycles/bit
• Data retention
10 years
• Guaranteed operating temperature range
40 to 85°C
• Package options:
8-pin plastic SOP (P-SOP8-200-1.27-T2K)
• RoHS (Restriction of hazardous substances) compliant
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MR44V064A Datasheet Preview

MR44V064A Datasheet

FeRAM

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PIN CONFIGURATION
8-pin plastic SOP
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
FEDR44V064A-02
MR44V064A
PIN DESCRIPTIONS
Pin Name
Description
A0 – A2
Address ( input )
Address pin indicates device address. When Address value is match the device address
code from SDA, the device will be selected. The address pins are pulled down internally.
SDA
Serial data input serial data output ( input / output )
SDA is a bi-directional line for I2C interface. The output driver is open-drain. A pull-up
resistor is required.
Serial Clock ( input )
SCL Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on
the rising edge and outputs occur on the falling edge.
Write protect ( input )
WP Write Protect pin controls write-operation to the memory. When WP is high, all address in
the memory will be protected. When WP is low, all address in the memory will be written.
WP pin is pulled down internally.
VCC, VSS
Power supply
Apply the specified voltage to VCC. Connect VSS to ground.
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Part Number MR44V064A
Description FeRAM
Maker LAPIS
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