PL613-21 Datasheet | Micrel Semiconductor

DESCRIPTION The PL613-21 is an advanced three PLL design based on Pico PLL, the world’s smallest programmable clock technology. This advanced technology allows the PL613 -21 to fit in to a small 3x3mm QFN package for high performance, low-power, small form-factor applications. By using the individual output buffer VDD pins, the PL613-21 can support multiple output voltage requirements. In addition, CLK1 has the ability to generate k Hz outputs and is ideal for generating 32.768k Hz outputs. The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding clock output is disabled using the PDB pins. The output drive strength can be individually programmed on each output to Low (4m A), Standard (8m A) or High (16m A) drive. In addition, the disabled state of the clock outputs can be programmed as Hi-Z or Active Low. Besides its small form factor and multiple outputs that can reduce overall system costs, the PL613 -21 offers superior phase noise, jitter and power consumption performance. Micrel Inc. - 2180 Fortune Drive - San Jose, CA 95131 - USA - tel +1(408) 944 -0800 - fax +1(408) 474-1000 - .micrel. Rev 8/11/10 Page 1 Ultra Low Power Pico PLL, Programmable 3-PLL Clock IC BLOCK DIAGRAM XIN/FIN XOUT Xtal FREF Osc FREF PLL1 VCO1 5-bit ÷ Odd/Even ÷ 1,2,4,8 CLK2 VDD2_3- CLK3 PDB2_3 PDB1 PDB4 FREF PLL2 VCO2 15-bit ÷ Odd/Even CLK1 VDD1- PLL3 VCO3 5-bit ÷ Odd/Even Programmable Function - Separate buffer VDD’s allow output level control (1.8V ~ 3.3V, ±10%) CLK4 VDD4- PACKAGE PIN ASSIGNMENT Name Package Pin # QFN-16L Type Description CLK1 1 O Programmable clock...