SY100S891 transceiver equivalent, 5-bit registered transceiver.
DESCRIPTION
s 25Ω cut-off bus outputs s 50Ω receiver outputs s Transmit and receive registers with separate clocks s 1500ps max. delay from CLK1 to Bus Outputs (BUS) s .
s 25Ω cut-off bus outputs s 50Ω receiver outputs s Transmit and receive registers with separate clocks s 1500ps max. delay from CLK1 to Bus Outputs (BUS) s 1500ps max. delay from CLK2 to Receiver Outputs (Q) s Individual bus enable pins s Internal 7.
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