SY10E195 chip equivalent, programmable delay chip.
s Up to 2ns delay range s Extended 100E VEE range of
–4.2V to
–5.5V s ≈20ps/digital step resolution s >1GHz bandwidth s On-chip cascade ci.
The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition.
The delay section consists of a chain of gates organized as shown .
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