SY89610L Key Features
- Accepts high jitter input clock signal and attenuates it to provide Ultra-Low Jitter and Phase Noise clock signal at the
- Output Frequency Range: 77.75MHz
- 694MHz
- Input Frequency Range: 19.44MHz
- 694MHz
- Phase Noise and Jitter performance
- <2psRMS Output Jitter Gen (12kHz-20MHz)
- Low Phase Noise: -80dBc/Hz at 1kHz offset
- CML patible output signal
- 3-pin input accepts an AC- or DC-coupled differential input (LVDS, LVPECL, and CML)