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Micron Technology

MT28F322P3 Datasheet Preview

MT28F322P3 Datasheet

FLASH MEMORY

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FLASH MEMORY
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
MT28F322P3
Low Voltage, Extended Temperature
FEATURES
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice versa
• Basic configuration:
Seventy-one erasable blocks
Bank a (8Mb for data storage)
Bank b (24Mb for program storage)
• VCC, VCCQ, VPP voltages
2.7V (MIN), 3.3V (MAX) VCC
2.2V (MIN), 3.3V (MAX) VCCQ
3.0V (TYP) VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns @ 2.7V VCC
• Page Mode read access
Eight-word page
Interpage read access: 70ns @ 2.7V
Intrapage read access: 30ns @ 2.7V
• Low power consumption (VCC = 3.3V)
Asynchronous/interpage READ < 15mA
Intrapage READ < 7mA
WRITE < 20mA (MAX)
ERASE < 25mA (MAX)
Standby < 15µA (TYP), 50µA (MAX) @ 3.3V
Automatic power save (APS) feature
• Enhanced write and erase suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
purposes
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
• Fast programming algorithm
VPP = 12V ±5%
BALL ASSIGNMENT
48-Ball FBGA
12
A A13 A11
3
A8
456
VPP WP# A19
7
A7
8
A4
B A14 A10 WE# RST# A18 A17
A5
A2
C A15 A12 A9 NC A20 A6 A3 A1
D A16 DQ14 DQ5 DQ11 DQ2 DQ8 CE#
A0
E VCCQ DQ15 DQ6 DQ12 DQ3 DQ9 DQ0
VSS
F VSS
DQ7 DQ13 DQ4
VCC DQ10 DQ1 OE#
Top View
(Ball Down)
NOTE: See page 7 for Ball Description Table.
See page 35 for mechanical drawing.
OPTIONS
MARKING
• Timing
70ns access
80ns access
• Boot Block Configuration
Top
Bottom
• Package
48-ball FBGA (6 x 8 ball grid)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
-70
-80
T
B
FJ
None
ET
Part Number Example:
MT28F322P3FJ-70 BET
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.




Micron Technology

MT28F322P3 Datasheet Preview

MT28F322P3 Datasheet

FLASH MEMORY

No Preview Available !

GENERAL DESCRIPTION
The MT28F322P3 is a high-performance, high-
density, nonvolatile memory solution that can
significantly improve system performance. This new
architecture features a two-memory-bank configura-
tion that supports background operation with no
latency.
A high-performance bus interface allows a fast page
mode data transfer; a conventional asynchronous bus
interface is provided as well.
The MT28F322P3 allows soft protection for blocks,
as read only, by configuring soft protection registers
with dedicated command sequences. For security pur-
poses, two 64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to moni-
tor the WSM status and to determine the progress of
the program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The device is manufactured using 0.18µm process
technology.
Please refer to Micron’s Web site (www.micron.com/
flash) for the latest data sheet.
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
ARCHITECTURE AND MEMORY
ORGANIZATION
The MT28F322P3 Flash device contains two sepa-
rate banks of memory (bank a and bank b) for simulta-
neous READ and WRITE operations.
The MT28F322P3 Flash memory is available in the
following bank segmentation configuration:
• Bank a comprises one-fourth of the memory
and contains 8 x 4K-word parameter blocks
and 15 x 32K-word blocks.
• Bank b represents three-fourths of the
memory, is equally sectored, and contains
48 x 32K-word blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F322P3FJ-70 BET
MT28F322P3FJ-70 TET
MT28F322P3FJ-80 BET
MT28F322P3FJ-80 TET
PRODUCT
MARKING
FW816
FW817
FW814
FW815
SAMPLE
MARKING
FX816
FX817
FX814
FX815
MECHANICAL
SAMPLE MARKING
FY816
FY817
FY814
FY815
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.


Part Number MT28F322P3
Description FLASH MEMORY
Maker Micron Technology
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