MT41K512M4 Key Features
- VDD = VDDQ = 1.35V (1.283-1.45V)
- Backward-patible to VDD = VDDQ = 1.5V ±0.075V
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT)
- Programmable CAS (READ) latency (CL)
- Programmable posted CAS additive latency (AL)
- Programmable CAS (WRITE) latency (CWL)