MT48H16M16LFBG sdram equivalent, 256m x 16 mobile sdram.
* Temperature Compensated Self Refresh (TCSR)
* Fully synchronous; all signals registered on positive edge of system clock
* Internal pipelined operation; col.
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Ea.
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