AS5SS512K36D
Description
The AS5SS512K36D is is a 3.3V, 512K x 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion.
Key Features
- Supports 133MHz bus operations with zero wait states -Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Registered inputs for Flow-Through operation
- Fast clock-to-output times -6.5ns (for 133 MHz device)* -8.5ns (for 100 MHz device)
- Single 3.3V -5% and +1-% power supply VDD
- Separate VDD for 3.3V or 2.5V I/O
- Clock Enable (CEN) pin to suspend operation
- Synchronous self-timed writes
- Available in 100-pin TSOP package.**
- Burst Capability - linear or interleaved burst order
