AS5SS128K36 Datasheet - Austin Semiconductor

AS5SS128K36 128K x 36 SSRAM SYNCHRONOUS ZBL SRAM FLOW-THRU OUTPUT

The Austin Semiconductor, Inc. Zero Bus Latency SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. ASI’s 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMS are optimized for 100 perce.

AS5SS128K36 Features

* High frequency and 100% bus utilization

* Fast cycle times: 11ns & 12ns

* Single +3.3V +5% power supply (VDD)

* Advanced control logic for minimum control signal interface

* Individual BYTE WRITE controls may be tied LOW

* Single R/W (READ/WRITE) con

AS5SS128K36_AustinSemiconductor.pdf