- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti.

M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are refe.

M2S56D20ATP

M2S56D20ATP-10

M2S56D20ATP-10L

M2S56D20ATP-75

M2S56D20ATP-75A

M2S56D20ATP-75AL

M2S56D20ATP-75L

M2S56D20AKT

M2S56D20AKT-10

M2S56D20AKT-10L

M2S56D20AKT-75

M2S56D20AKT-75A

M2S56D20AKT-75AL