- Vdd=Vddq=2.5v±0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti.

M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registere.

M2S56D30TP-10

M2S56D30TP

M2S56D30AKT

M2S56D30AKT-10

M2S56D30AKT-10L

M2S56D30AKT-75

M2S56D30AKT-75A

M2S56D30AKT-75AL

M2S56D30AKT-75L

M2S56D30ATP

M2S56D30ATP-10

M2S56D30ATP-10L

M2S56D30ATP-75