M2V28S30TP
Description
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit.
Key Features
- And does not support Low-Power (L) version
- 1.0 - Add PC133 Specification
