M2V28S30TP - 128M Synchronous DRAM

Product Overview

Mitsubishi

Datasheet Details

Part number	M2V28S30TP
Manufacturer	Mitsubishi
File Size	639.70 KB
Description	128M Synchronous DRAM
Datasheet	M2V28S30TP Datasheet
Additional preview pages of the M2V28S30TP datasheet.

Product details

Description

M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit.

Features

M2V28S20/30/40TP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max. ) (Single Bank) (Max. ) (Min. ) (Min. ) (Min. ) (Max. ) (CL=3) (Min. ) V28S20 V28S30 V28S40 Icc6 Self Refresh Current -6 7.5ns 45ns 20ns 5.4ns 67.5ns 120mA 130mA 2mA -7 10ns 50ns 20ns 6ns 70ns 115mA 120mA 135mA 2mA -8 10ns 50ns 20ns 6ns 70ns 115mA 120mA 135mA 2mA Active to Precharge Command Period - Single 3.3V ±0.3V power supply - Max. Clock fr.

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Published: May 2, 2005 |