M2V28S30TP - 128M Synchronous DRAM

Mitsubishi

Datasheet Details

M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with.

M2V28S20/30/40TP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max. ) (Single Bank) (Max. ) (Min. ) (Min. ) (Min. ) (Max. ) (CL=3) (Min. ) V28S20 V28S30 V28S40 Icc6 Self Refresh Current -6 7.5ns 45ns 20ns 5.4ns 67.5ns 120mA 130mA 2mA -7 10ns 50ns 20ns 6ns 70ns 115mA 120mA 135mA 2mA -8 10ns 50ns 20ns 6ns 70ns 115mA 120mA 135mA 2mA Active to Precharge Command Period - Single 3.3V ±0.3V power supply - Max. Clock fr.

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