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Mitsubishi

M5M4V64S30ATP-8 Datasheet Preview

M5M4V64S30ATP-8 Datasheet

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

No Preview Available !

SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
Vdd
DQ0
VddQ
NC
1
2
3
4
54 Vss
53 DQ7
52 VssQ
51 NC
M5M4V64S30ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
DQ1
VssQ
NC
5
6
7
50 DQ6
49 VddQ
48 NC
in computer systems.
DQ2
VddQ
NC
8
9
10
47 DQ5
46 VssQ
45 NC
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz / 100MHz / 83MHz
DQ3
VssQ
NC
Vdd
NC
/WE
11
12
13
14
15
16
44 DQ4
43 VddQ
42 NC
41 Vss
40 NC (Vref)
39 DQM
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8 (programmable)
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
17
18
19
20
21
22
23
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
- Burst type- sequential / interleave (programmable)
- Column access - random
- Auto precharge / All bank precharge controlled by A10
A1 24
A2 25
A3 26
Vdd 27
31 A6
30 A5
29 A4
28 Vss
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A8
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
M5M4V64S30ATP-8
M5M4V64S30ATP-10
M5M4V64S30ATP-12
Max.
Frequency
125MHz
100MHz
83MHz
CLK Access
Time
6ns
8ns
8ns
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-7
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
1




Mitsubishi

M5M4V64S30ATP-8 Datasheet Preview

M5M4V64S30ATP-8 Datasheet

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

No Preview Available !

SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
BLOCK DIAGRAM DQ0-7(0-3)
I/O Buffer
Memory Array Memory Array Memory Array Memory Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
A0-11 BA0,1
Clock Buffer
/CS /RAS /CAS /WE DQM
CLK CKE
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 5M 4 V 64 S 3 0 A TP - 8
Cycle Time (min.) 8: 8ns, 10: 10ns, 12: 12ns
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column, 1: 2N-rule
Organization 2n 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 64:64M bits
Interface S: SSTL, V:LVTTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
2


Part Number M5M4V64S30ATP-8
Description 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Maker Mitsubishi
Total Page 30 Pages
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