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V58C265164S - 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

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Datasheet Details

Part number V58C265164S
Manufacturer Mosel Vitelic Corp
File Size 451.71 KB
Description 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16
Datasheet download datasheet V58C265164S Datasheet

General Description

The V58C265164S is a four bank DDR DRAM organized as 4 banks x 1Mbit x 16.

The V58C265164S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock.

I/O transactions are possible on both edges of DQS.

Overview

MOSEL VITELIC V58C265164S 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 PRELIMINARY 4 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK2) 250 MHz 4 ns 4.8 ns 6 ns 45 225 MHz 4.5 ns 5.4 ns 6.75 ns 5 200 MHz 5 ns 6 ns 7.5 ns 55 183 MHz 5.5 ns 6.6 ns 8.

Key Features

  • I 4 banks x 1Mbit x 16 organization I High speed data transfer rates with system frequency up to 250 MHz I Data Mask for Write Control (DM) I Four Banks controlled by BA0 & BA1 I Programmable CAS Latency: 2, 2.5, 3 I Programmable Wrap Sequence: Sequential or Interleave I Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type I Automatic and Controlled Precharge Command I Suspend Mode and Power Down Mode I Auto Refresh and Self Refresh I Refresh Interval: 4096 cycles/.

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