MC88915T
description on page 11). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0- Q4, Q5 and Q/2 into a high impedance state (3- state). After the OE/RST pin goes back high Q0- Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse. A lock indicator output (LOCK) will go high when the loop is in steady- state phase and frequency lock. The LOCK output will go low if phase- lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a SYNC signal and full 5V VCC.
Features
- Five Outputs (Q0- Q4) with Output- Output Skew < 500 ps each being phase and frequency locked to the SYNC input
- The phase variation from part- to- part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t PD specification, which defines the part- to- part skew)
- Input/Output phase- locked frequency ratios...
