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MCM62110 Datasheet

32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

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MCM62110 pdf
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM62110/D
32K x 9 Bit Synchronous Dual I/O
or Separate I/O Fast Static RAM
with Parity Checker
MCM62110
The MCM62110 is a 294,912 bit synchronous static random access memory
organized as 32,768 words of 9 bits, fabricated using Motorola’s high–perfor-
mance silicon–gate CMOS technology. The device integrates a 32K x 9 SRAM
core with advanced peripheral circuitry consisting of address registers, two sets
of input data registers, two sets of output latches, active high and active low chip
enables, and a parity checker. The RAM checks odd parity during RAM read
cycles. The data parity error (DPE) output is an open drain type output which indi-
cates the result of this check. This device has increased output drive capability
supported by multiple power pins. In addition, the output levels can be either 3.3 V
or 5 V TTL compatible by choice of the appropriate output bus power supply.
The device has both asynchronous and synchronous inputs. Asynchronous
inputs include the processor output enable (POE), system output enable (SOE), and
the clock (K).
The address (A0 – A14) and chip enable (E1 and E2) inputs are synchronous
and are registered on the falling edge of K. Write enable (W), processor input
enable (PIE) and system input enable (SIE) are registered on the rising edge
of K. Writes to the RAM are self–timed.
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP
have input data registers triggered by the rising edge of the clock. These pins also
have three–state output latches which are transparent during the high level of the
clock and latched during the low level of the clock.
This device has a special feature which allows data to be passed through the
RAM between the system and processor ports in either direction. This streaming
is accomplished by latching in data from one port and asynchronously output
enabling the other port. It is also possible to write to the RAM while streaming.
Additional power supply pins have been utilized for maximum performance. The
output buffer power (VCCQ) and ground pins (VSSQ) are electrically isolated from
VSS and VCC, and supply power and ground only to the output buffers. This allows
connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V output levels
are chosen, the output buffer impedance in the ‘‘high’’ state is approximately equal
to the impedance in the ‘‘low’’ state thereby allowing simplified transmission line ter-
minations.
The MCM62110 is available in a 52–pin plastic leaded chip carrier (PLCC).
This device is ideally suited for pipelined systems and systems with multiple
data buses and multiprocessing systems, where a local processor has a bus iso-
lated from a common system bus.
Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level
Compatibility
Fast Access and Cycle Times: 15/17/20 ns Max
Self–Timed Write Cycles
Clock Controlled Output Latches
Address, Chip Enable, and Data Input Registers
Common Data Inputs and Data Outputs
Dual I/O for Separate Processor and Memory Buses
Separate Output Enable Controlled Three–State Outputs
Odd Parity Checker During Reads
Open Drain Output on Data Parity Error (DPE) Allowing Wire–ORing of
Outputs
High Output Drive Capability: 85 pF/Output at Rated Access Time
High Board Density 52 Lead PLCC Package
Active High and Low Chip Enables for Easy Memory Depth Expansion
Can be used as Separate I/O x9
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
E2
E1
PDQ7
SDQ7
VSSQ
PDQ5
SDQ5
VCCQ
PDQ3
SDQ3
VSSQ
PDQ1
SDQ1
7 6 5 4 3 2 1 52 51 50 49 48 47
8 46
9 45
10 44
11 43
12 42
13 41
14 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A14 . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E1 . . . . . . . . . . . . . Active Low Chip Enable
E2 . . . . . . . . . . . . . Active High Chip Enable
PIE . . . . . . . . . . . . . Processor Input Enable
SIE . . . . . . . . . . . . . . . System Input Enable
POE . . . . . . . . . . Processor Output Enable
SOE . . . . . . . . . . . . . System Output Enable
DPE . . . . . . . . . . . . . . . . . . Data Parity Error
PDQ0 – PDQ7 . . . . . . . Processor Data I/O
PDQP . . . . . . . . . . . Processor Data Parity
SDQ0 – SDQ7 . . . . . . . . . System Data I/O
SDQP . . . . . . . . . . . . . System Data Parity
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VCCQ . . . . . . Output Buffer Power Supply
VSSQ . . . . . . . . . . . . Output Buffer Ground
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC VCCQ at all times including power up.
PDQP
SDQP
VSSQ
PDQ6
SDQ6
VCCQ
PDQ4
SDQ4
PDQ2
SDQ2
VSSQ
PDQ0
SDQ0
REV 3
5/95
M© OMoTtoOroRla,OInLc.A19F94AST SRAM
MCM62110
1


Motorola Electronic Components Datasheet

MCM62110 Datasheet

32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

No Preview Available !

MCM62110 pdf
BLOCK DIAGRAM
K
A0 – A14
32K × 9 ARRAY
DPE
DATA
REGISTER
PARITY
CHECK
WRITE
DRIVER
PDQ0 – PDQ7, PDQP
DATA
REGISTER
9
DATA
LATCH
POE
9
SENSE
DATA
DATA
AMPLIFIER
LATCH
REGISTER
W
E1
E2 9
PIE
SIE
SDQ0 – SDQ7, SDQP
SOE
FUNCTIONAL TRUTH TABLE (See Notes 1 and 2)
Memory Subsystem
W PIE SIE POE SOE Mode
Cycle
1 1 1 0 1 Read
Processor Read
1 1 1 1 0 Read
Copy Back
1 1 1 0 0 Read
Dual Bus Read
1 X X 1 1 Read
NOP
X 0 0 X X N/A
NOP
0 0 1 1 1 Write Processor Write Hit
0 1 0 1 1 Write
Allocate
0 0 1 1 0 Write
Write Through
0 1 0 0 1 Write Allocate With Stream
1 0 1 1 0 N/A
Cache Inhibit Write
1 1 0 0 1 N/A
Cache Inhibit Read
0 1 1 X X N/A
NOP
X 0 1 0 0 N/A
Invalid
X 0 1 0 1 N/A
Invalid
X 1 0 0 0 N/A
Invalid
X 1 0 1 0 N/A
Invalid
PDQ0 – PDQ7,
PDQP Output
Data Out
High–Z
Data Out
High–Z
High–Z
Data In
High–Z
Data In
Stream Data
Data In
Stream Data
High–Z
Data In
Data In
Stream
High–Z
SDQ0 – SDQ7,
SDQP Output
High–Z
Data Out
Data Out
High–Z
High–Z
High–Z
Data In
Stream Data
Data In
Stream Data
Data In
High–Z
Stream
High–Z
Data In
Data In
DPE
Parity Out
Parity Out
Parity Out
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes
3, 4
3, 4
3, 4
2, 5
2, 6
2
2, 7
2, 7
2, 7
2, 7
5
2, 8
2, 8
2, 8
2, 8
NOTES:
1. A ‘0’ represents an input voltage VIL and a ‘1’ represents an input voltage VIH. All inputs must satisfy the specified setup and hold times
for the falling or rising edge of K. Some entries in this truth table represent latched values. This table assumes that the chip is selected (i.e.,
E1 = 0 and E2 = 1) and VCC current is equal to ICCA. If this is not true, the chip will be in standby mode, the VCC current will equal ISB1 or ISB2
DPE will default to 1 and all RAM outputs will be in High–Z. Other possible combinations of control inputs not covered by this note or the table
above are not supported and the RAM’s behavior is not specified.
2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are High–Z.
3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM.
4. DPE is registered on the rising edge of K at the beginning of the following clock cycle
5. No RAM cycle is performed.
6. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and PDQP
or SDQ0 – SDQ7 and SPDQ), and written into the RAM.
7. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other I/O
port.
8. Data contention will occur.
MCM62110
2
MOTOROLA FAST SRAM


Part Number MCM62110
Description 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker
Maker Motorola
Total Page 12 Pages
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