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Motorola Electronic Components Datasheet

MTB75N03HDL Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB75N03HDL/D
Advanced Information
HDTMOS E-FET.
High Density Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
D
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
G
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Ultra Low RDS(on), High–Cell Density, HDTMOS
Short Heatsink Tab Manufactured — Not sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
S
MTB75N03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
75 AMPERES
25 VOLTS
RDS(on) = 9 mOHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS
VDGR
VGS
VGSM
25
25
± 15
± 20
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
ID 75
ID 59
IDM 225
PD 125
1.0
2.5
Operating and Storage Temperature Range
– 55 to 150
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL
(1) When mounted with the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
280
1.0
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB75N03HDL Datasheet

TMOS POWER FET

No Preview Available !

MTB75N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
(Cpk 2.0) (3) V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
(Cpk 3.0) (3)
IDSS
IGSS
VGS(th)
Static Drain–Source On–Resistance
(VGS = 5.0 Vdc, ID = 37.5 Adc)
(Cpk 2.0) (3)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(VDS= 15 Vdc, ID = 75 Adc,
VGS = 5.0 Vdc,
RG = 4.7 )
(VDS = 24 Vdc, ID = 75 Adc,
VGS = 5.0 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 75 Adc, VGS = 0 Vdc)
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
Reverse Recovery Time
(IS = 75 Adc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk = 3 x SIGMA
trr
ta
tb
QRR
Min
25
1.0
15
Typ Max Unit
Vdc
——
mV/°C
µAdc
— 100
— 500
— 100 nAdc
Vdc
1.5 2.0
mV/°C
m
6.0 9.0
Vdc
— 0.68
— 0.6
55 — mhos
4025
1353
307
5635
1894
430
pF
24 48
493 986
60 120
149 300
61 122
14 28
33 66
27 54
ns
nC
0.97
0.87
58
27
30
0.088
1.1
Vdc
ns
µC
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB75N03HDL
Description TMOS POWER FET
Maker Motorola
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