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Motorola Electronic Components Datasheet

MTB75N05HD Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB75N05HD/D
Designer's Data Sheet
HDTMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
G
D
S
MTB75N05HD
Motorola Preferred Device
TMOS POWER FET
75 AMPERES
50 VOLTS
RDS(on) = 9.5 m
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
50 Volts
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR
50
Gate–to–Source Voltage — Continuous
VGS
± 20
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 75 Amps
ID 65
IDM 225
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (minimum footprint, FR–4 board)
PD 125 Watts
1.0 W/°C
2.5 Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 )
EAS 500 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (minimum footprint, FR–4 board)
RθJC
RθJA
RθJA
1.0 °C/W
62.5
50
Maximum Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB75N05HD Datasheet

TMOS POWER FET

No Preview Available !

MTB75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 250 µAdc)
Temperature Coefficient (Positive)
(Cpk 2)(2)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 50 V, VGS = 0)
(VDS = 50 V, VGS = 0, TJ = 125°C)
Gate–Body Leakage Current
(VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
(Cpk 1.5)(2)
Static Drain–to–Source On–Resistance(3)
(VGS = 10 Vdc, ID = 20 Adc)
Drain–to–Source On–Voltage (VGS = 10 Vdc)(3)
(ID = 75 A)
(ID = 20 Adc, TJ = 125°C)
(Cpk 3.0)(2)
Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 V, VGS = 0, (Cpk 2.0)(2)
f = 1.0 MHz)
(Cpk 2.0)(2)
(Cpk 2.0)(2)
SWITCHING CHARACTERISTICS (4)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 25 V, ID = 75 A,
VGS = 10 V,
RG = 9.1 )
Gate Charge
(VDS = 40 V, ID = 75 A,
VGS = 10 V)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 75 A, VGS = 0) (Cpk 10)(2)
(IS = 20 A, VGS = 0)
(IS = 20 A, VGS = 0, TJ = 125°C)
Reverse Recovery Time
(IS = 37.5 A, VGS = 0,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25from package to center of die)
IDSS
IGSS
VGS(th)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
trr
ta
tb
QRR
LD
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
LS
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Reflects Typical Values. Cpk = ABSOLUTE VALUE OF (SPEC – AVG) / 3 * SIGMA).
(3) For accurate measurements, good Kelvin contact required.
(4) Switching characteristics are independent of operating junction temperature.
Min
50
2.0
15
Typ Max Unit
— — Vdc
54.9 — mV/°C
µAdc
— 10
— 100
nAdc
— 100
— 4.0 Vdc
6.3 — mV/°C
m
7.0 9.5
Vdc
0.63 —
— 0.34
— — mhos
2600
1000
230
2900
1100
275
pF
15 30
170 340
70 140
100 200
71 100
13 —
33 —
26 —
ns
nC
0.97 — Vdc
0.80 1.00
0.68 —
57 — ns
40 —
17 —
0.17 —
µC
nH
3.5 —
4.5 —
7.5 —
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB75N05HD
Description TMOS POWER FET
Maker Motorola
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