SN54LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Motorola Inc

Datasheet Details

individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. DUAL JK.

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