NE24200
NE24200 is C to Ka BAND SUPER LOW NOISE AMPLIFIER N-CHANNEL HJ-FET CHIP manufactured by NEC.
DESCRIPTION
NE32400 and NE24200 are Hetero Junction FET chip that utilizes the hetero junction between Si-doped Al Ga As and undoped In Ga As to create high mobility electrons. Its excellent low noise and high associated gain make it suitable for mercial systems, industrial and space applications.
FEATURES
- Super Low Noise Figure & High Associated Gain NF = 0.6 d B TYP., Ga = 11.0 d B TYP. at f = 12 GHz
- Gate Length : Lg = 0.25 µm
- Gate Width : Wg = 200 µm
ORDERING INFORMATION
PART NUMBER NE32400 NE24200 Standard (Grade D) Grade C and B (B is special order) QUALITY GRADE APPLICATIONS mercial Industrial, space
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Drain to Source Voltage Gate to Source Voltage Drain Current Total Power Dissipation Channel Temperature Storage Temperature VDS VGS ID Ptot- Tch Tstg 4.0
- 3.0 IDSS 200 175
- 65 to +175 V V m A m W ˚ C ˚ C
- Chip mounted on a Alumina heatsink (size: 3 × 3 × 0.6t)
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)
PARAMETER Gate to Source Leak Current Saturated Drain Current Gate to Source Cutoff Voltage Transconductance Thermal Resistance Noise Figure Associated Gain SYMBOL IGSO IDSS VGS(off) gm Rth- NF Ga MIN.
- 15
- 0.2 45
- - 10.0 TYP. 0.5 40
- 0.8 60
- 0.6 11.0 MAX. 10 70
- 2.0
- 260 0.7
- UNIT TEST CONDITIONS VGS =
- 3 V VDS = 2 V, VGS = 0 V VDS = 2 V, ID = 100 µA VDS = 2 V, ID = 10 m A channel to case VDS = 2 V, ID = 10 m A, f = 12 GHz
µA m A V m S ˚C/W d B d B
RF performance is determined by packaging and testing 10 chips per wafer. Wafer rejection criteria for standard devices is 2 rejects per 10 samples.
Document No. P11345EJ2V0DS00 (2nd edition) (Previous No. TD-2358) Date Published May 1996 P Printed in Japan
©
NE32400, NE24200
CHIP DIMENSIONS (Unit: µm)
400 56 112
61 53
Drain...
