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UPD44165362 - (UPD44165082/182/362) 18M-BIT QDRII SRAM 2-WORD BURST OPERATION

This page provides the datasheet information for the UPD44165362, a member of the UPD44165082 (UPD44165082/182/362) 18M-BIT QDRII SRAM 2-WORD BURST OPERATION family.

Datasheet Summary

Description

technology using full CMOS six-transistor memory cell.

Features

  • 1.8 ± 0.1 V power supply and HSTL I/O.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Separate independent read and write data ports with concurrent transactions.
  • 100% bus utilization DDR READ and WRITE operation.
  • Two-tick burst for low DDR transaction size.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two output clocks (C and /C) for precise flight time and clock skew.

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Datasheet Details

Part number UPD44165362
Manufacturer NEC
File Size 385.19 KB
Description (UPD44165082/182/362) 18M-BIT QDRII SRAM 2-WORD BURST OPERATION
Datasheet download datasheet UPD44165362 Datasheet
Additional preview pages of the UPD44165362 datasheet.

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Full PDF Text Transcription

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DATA SHEET MOS INTEGRATED CIRCUIT µPD44165082, 44165182, 44165362 18M-BIT QDRTMII SRAM 2-WORD BURST OPERATION Description The µPD44165082 is a 2,097,152-word by 8-bit, the µPD44165182 is a 1,048,576-word by 18-bit and the µPD44165362 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44165082, µPD44165182 and µPD44165362 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.
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