UPD4483362 Datasheet | NEC

PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4483362 8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE Description The µPD4483362 is a 262,144 words by 36 bits synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The µPD4483362 is suitable for applications which require synchronous operation, high-speed, low voltage, highdensity memory and wide bit configuration, such as cache and buffer memory. The µPD4483362 is packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features - Fully synchronous operation - HSTL Input / Output levels - Fast clock access time : 3.8 ns (133 MHz) - Asynchronous output enable control : /G - Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9) - mon I/O using three-state outputs - Internally self-timed write cycle - Late write with 1 dead cycle between Read-Write - 3.3 V (Chip) / 1.5 V (I/O) supply - 100-pin PLASTIC LQFP package, 14 mm x 20 mm - Sleep Mode : ZZ (Enables sleep mode, active high) Ordering Information Part number Access time 3.8 ns Clock frequency 133 MHz Package 100-pin PLASTIC LQFP (14 x 20) µPD4483362GF-A75 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14440EJ1V0DS00 (1st edition) Date Published April 2001 NS CP(K) Printed in Japan © µPD4483362 Pin Configuration (Marking Side) /xxx indicates active low signal. 100-pin PLASTIC LQFP (14 x 20) [ µPD4483362GF ] SA17 /SBd /SBb /SBa VREF /SBc SA6 SA7 SA8 SA9 /SW VDD...