UPD4481361 Description
DATA SHEET MOS INTEGRATED CIRCUIT µPD4481161, 4481181, 4481321, 4481361 8M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION .UPD4481361 Features
* Low voltage core supply : VDD = 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y) VDD = 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y)UPD4481361 Applications
* which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. Whe
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