UPD4481362 Description
DATA SHEET MOS INTEGRATED CIRCUIT µPD4481162, 4481182, 4481322, 4481362 8M-BIT ZEROSBTM SRAM PIPELINED OPERATION .UPD4481362 Features
* Low voltage core supply : VDD = 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y) VDD = 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y)UPD4481362 Applications
* which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. Whe
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