Overview: SSSS7777LLLL1111666613318668UUUU2222MMMM 551122KKxx3366&&11MMxx1188DDDDRRIII+I+CCIOIOBBLL22SSRRAAMMww//OODDTT 18Mb DDRII+ CIO BL2 w/ ODT SRAM Specification
(2.5 Clock Read Latency)
165FBGA with Pb & Pb Free
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Rev. 1.2 Apr. 2013 -1- S7L1636U2M S7L1618U2M 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM w/ ODT Document Title
512Kx36 & 1Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM w/ ODT (2.5 Clock Read Latency) Revision History Rev. No. History 1.0 Final spec release 1.1 Add 400MHz speed binning 1.2 Change Thermal Resistance JA value from 20.8C/W to 16.3C/W Draft Date
Feb. 2013 Mar. 2013 Apr. 2013 Remark
Final Final Final Rev. 1.2 Apr. 2013 -2- S7L1636U2M S7L1618U2M 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM w/ ODT 512Kx36 & 1Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM w/ ODT (2.
