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S7L3236U2M - 1Mx36 & 2Mx18 DDRII+ CIO BL2 SRAM w/ ODT

Datasheet Summary

Description

The S7L3236U2M and S7L3218U2M are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

They are organized as 1,048,576 words by 36bits for S7L3236U2M and 2,097,152 words by 18 bits for S7L3218U2M.

Features

  • Key Parameters.
  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency: 2.5 cloc.

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Datasheet Details

Part number S7L3236U2M
Manufacturer NETSOL
File Size 352.89 KB
Description 1Mx36 & 2Mx18 DDRII+ CIO BL2 SRAM w/ ODT
Datasheet download datasheet S7L3236U2M Datasheet
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Full PDF Text Transcription

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SS77LL33223366UU22MM SS77LL33221188UU22MM 11MMxx3366 && 22MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM ww// OODDTT 36Mb DDRII+ CIO BL2 w/ ODT SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO NETSOL PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN NETSOL PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Netsol products, contact your nearest Netsol office. 2.
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