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S7S3209U4M Datasheet 1mx36 & 2mx18 & 4mx9 Quadruple-ii+ Bl4 Sram

Manufacturer: NETSOL

Overview: S7S3236U4M S7S3218U4M S7S3209U4M 11MMxx3366 && 22MMxx1188 && 44MMxx99 QQuuaaddrruuppllee--IIII++ BBLL44 SSRRAAMM 36Mb Quadruple-II+ BL4 SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO NETSOL PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN NETSOL PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Netsol products, contact your nearest Netsol office. 2. Netsol products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Netsol reserves the rights to change products or specification without notice. Rev. 1.2 Apr. 2013 -1- S7S3236U4M S7S3218U4M S7S3209U4M 1Mx36 & 2Mx18 & 4Mx9 Quadruple-II+ BL4 SRAM Document Title 1Mx36 & 2Mx18 & 4Mx9 - Bit Quadruple-II+ Burst Length of 4 SRAM (2.5 Clock Read Latency) Revision History Rev. No. History 0.0 Initial Draft 1.0 Final spec release Add current spec value 1.1 Add 400MHz speed binning 1.2 Change Thermal Resistance θJA value from 20.8°C/W to 16.3°C/W Draft Date Sep. 2012 Feb. 2013 Remark Preliminary Final Mar. 2012 Apr. 2013 Final Final Rev. 1.2 Apr. 2013 -2- S7S3236U4M S7S3218U4M S7S3209U4M 1Mx36 & 2Mx18 & 4Mx9 Quadruple-II+ BL4 SRAM 1Mx36 & 2Mx18 & 4Mx9 - Bit Quadruple-II+ Burst Length of 4 SRAM (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
  • Separate independent read and write data ports with concurrent read and write operation.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency: 2.5 clock cycle.

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