Description
The 74F113, dual negative edge-triggered JK-type flip-flop,.
Features
- individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP. TYPE 74F113 TYPICAL fmax 100MHz
PIN CONFIGURATION
CP0 K0 J0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC CP1 K1 J1 SD1 Q1 Q1
SF00140
TYPICAL SUPPLY CURRENT (TOTAL) 15mA
ORDERING INFORMATION
ORDE.
