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74HC138 - 3-to-8 line decoder/demultiplexer

General Description

The 74HC138;

74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

The device

Overview

74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev.

6 — 28 December 2015 Product data sheet 1.

Key Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC138: CMOS level.
  • For 74HCT138: TTL level.
  • Demultiplexing capability.