Description
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).
Features
- Wide supply voltage range from 2.0 to 6.0 V.
- CMOS low power dissipation.
- High noise immunity.
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
- Demultiplexing capability.
- Multiple input enable for easy expansion.
- Ideal for memory chip select decoding.
- Active LOW mutually exclusive outputs.
- Input levels:.
- For 74HC138: CMOS level.
- For 74HCT138: TTL level.
- Complies with JEDEC.
74HC138 Datasheet
