Description
The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).
Features
- Combines 3-to-8 decoder with 3-bit latch.
- Multiple input enable for easy expansion or independent controls.
- Active LOW mutually exclusive outputs.
- Wide supply voltage range from 2.0 to 6.0 V.
- CMOS low power dissipation.
- High noise immunity.
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
- Complies with JEDEC standards.
- JESD8C (2.7 V to 3.6 V).
- JESD7A (2.0 V to 6.0 V).
- ESD protecti.
74HC137 Datasheet
