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74HC137 - 3-to-8 line decoder/demultiplexer

General Description

The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

Key Features

  • Combines 3-to-8 decoder with 3-bit latch.
  • Multiple input enable for easy expansion or independent controls.
  • Active LOW mutually exclusive outputs.
  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A (2.0 V to 6.0 V).
  • ESD protecti.

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Datasheet Details

Part number 74HC137
Manufacturer Nexperia
File Size 269.07 KB
Description 3-to-8 line decoder/demultiplexer
Datasheet download datasheet 74HC137 Datasheet

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74HC138 3-to-8 line decoder/demultiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 5 — 4 August 2021 Product data sheet 1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores the data that was present before the transition in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable inputs control the state of the outputs independently of the address inputs or latch operation. All outputs will be HIGH unless E1 is LOW and E2 is HIGH. Inputs include clamp diodes.