HEF4020B
DESCRIPTION
The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0, O3 to O13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. A feature of the HEF4020B is: high speed (typ. 35 MHz at VDD = 15 V).
HEF4020B MSI
Fig.1 Functional diagram.
HEF4020BP(N): HEF4020BD(F): HEF4020BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America PINNING Fig.2 Pinning diagram. CP MR O0, O3 to O13 clock input (HIGH to LOW edge triggered) master reset input (active HIGH) parallel outputs
FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
Philips Semiconductors
Product specification
14-stage binary counter
HEF4020B...
