SAA7212
Overview
- Single external Synchronous DRAM organized as 1 M × 16 interfacing at 81 MHz. Due to efficient memory use in MPEG decoding, more than 1 Mbit available for graphics
- Fast 16-bit data + 8-bit address interface with external controller on 27 MHz. Sustained data rate to external SDRAM ≤9 Mbytes/s in bursts of 128 bytes
- Dedicated input for audio and video in PES or ES in byte wide. Data input rate: ≤9 Mbytes/s in byte mode. Accompanying strobe signals distinguish between audio and video data
- Dedicated compressed data input compatible with the VLSI VES2020/2030 demultiplexers; video is received in byte format and audio serially
- Audio and/or video can also be input via the CPU interface in PES/ES in 8 or 16-bit parallel format up to a peak data rate of 9 Mbytes/s
- Single 27 MHz external clock for time base reference and internal processing. Internal system time base at 90 kHz can be synchronized via CPU port. All required decoding and presentation clocks are generated internally
- Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks
- Boundary scan testing implemented
- External SDRAM self test
- Supply voltage 3.3 V
