74AUP2G17 Description
The 74AUP2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS patible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF.
74AUP2G17 Key Features
- 10 January 2008