NT5CC256M8GN Datasheet, Nanya

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential c.

The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchr.

The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 2,147,483,648 bits. It is internally configured as an octal-bank DRAM. The 2Gb chip is organized as 64Mbit x 4 I/O x 8 bank and 32Mbit x 8 I/O x 8 banks .