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National Semiconductor Electronic Components Datasheet

54ABT377 Datasheet

Octal D-Type Flip-Flop

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July 1998
54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’ABT273 for master reset version
n See ’ABT373 for transparent latch version
n See ’ABT374 for TRI-STATE® version
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Disable time less than enable time to avoid bus
contention
n Standard Microcircuit Drawing (SMD) 5962-9314801
Ordering Code:
Military
54ABT377J-QML
54ABT377W-QML
54ABT377E-QML
Connection Diagram
Package
Number
J20A
W20A
E20A
Pin Assignment for
DIP and Cerpack
Package Description
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Pin Assignment for LCC
DS100216-1
DS100216-11
Pin
Names
D0– D7
CE
CP
Q0– Q7
Description
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100216
www.national.com


National Semiconductor Electronic Components Datasheet

54ABT377 Datasheet

Octal D-Type Flip-Flop

No Preview Available !

Truth Table
Logic Diagram
Mode Select-Function Table
Operating Mode
Load “1”
Inputs
CP CE Dn
Ih
Output
Qn
H
Load “0”
II
L
Hold
h X No Change
(Do Nothing)
X H X No Change
H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L = LOW Voltage Level
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X = Immaterial
= LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
DS100216-3
www.national.com
2


Part Number 54ABT377
Description Octal D-Type Flip-Flop
Maker National Semiconductor
Total Page 8 Pages
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