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54ACT112 - Dual JK Negative Edge-Triggered Flip-Flop

Description

The ’ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs.

Synchronous state changes are initiated by the falling edge of the clock.

Triggering occurs at a voltage level of the clock and is not directly related to the transition time.

Features

  • n ’ACT112 has TTL-compatible inputs n Outputs source/sink 24 mA n Standard Microcircuit Drawing (SMD) 5962-8995001 Connection Diagram Pin Assigment for DIP and Flatpack Pin.

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www.DataSheet4U.com 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop September 1998 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.
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