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54ACT373 - Octal Transparent Latch

Download the 54ACT373 datasheet PDF. This datasheet also covers the 54AC373 variant, as both devices belong to the same octal transparent latch family and are provided as variant models within a single manufacturer datasheet.

Description

The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications.

The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.

When LE is LOW, the data that meets the setup time is latched.

Features

  • n n n n n n ICC and IOZ reduced by 50% Eight latches in a single package TRI-STATE outputs for bus interfacing Outputs source/sink 24 mA ’ACT373 has TTL-compatible inputs Standard Microcircuit Drawing (SMD).
  • ’AC373: 5962-87555.
  • ’ACT373: 5962-87556 Logic Symbols IEEE/IEC DS100329-1 DS100329-2 Pin Names D0.
  • D7 LE OE O0.
  • O7.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (54AC373_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
54ACT3301 Monolithic crystal controlled CMOS oscillator Silicon Supplies
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54ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES Texas Instruments
54ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES Texas Instruments
54ACT11010 Triple 3-Input Positive-NAND Gates Texas Instruments

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
54ACT374 Octal D Flip-Flop
54ACT377 Octal D Flip-Flop
54ACT00 Quad 2-Input NAND Gate
54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
54ACT112 Dual JK Negative Edge-Triggered Flip-Flop

Full PDF Text Transcription

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www.DataSheet4U.com 54AC373 • 54ACT373 Octal Transparent Latch with TRI-STATE Outputs August 1998 54AC373 • 54ACT373 Octal Transparent Latch with TRI-STATE ® Outputs General Description The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
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