74F377
Description
The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The mon buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Key Features
- Y Ideal for addressable register applications Y Clock enable for address and data synchronization
