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National Semiconductor Electronic Components Datasheet

74F377 Datasheet

Octal D Flip-Flop with Clock Enable

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May 1995
54F 74F377
Octal D Flip-Flop with Clock Enable
General Description
The ’F377 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs The common buffered
Clock (CP) input loads all flip-flops simultaneously when the
Clock Enable (CE) is LOW
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop’s Q out-
put The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable opera-
tion
Features
Y Ideal for addressable register applications
Y Clock enable for address and data synchronization
applications
Y Eight edge-triggered D flip-flops
Y Buffered common clock
Y See ’F273 for master reset version
Y See ’F373 for transparent latch version
Y See ’F374 for TRI-STATE version
Y Guaranteed 4000V minimum ESD protection
Commercial
74F377PC
74F377SC (Note 1)
74F377SJ (Note 1)
Military
54F377DM (QB)
54F377FM (QB)
54F377LM (QB)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Logic Symbols
IEEE IEC
TL F 9525 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9525
TL F 9525 – 4
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F377 Datasheet

Octal D Flip-Flop with Clock Enable

No Preview Available !

Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
Unit Loading Fan Out
Pin Names
Description
D0 – D7
CE
CP
Q0 – Q7
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
TL F 9525–2
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Operating Mode
Load ‘‘1’’
Load ‘‘0’’
Hold
(Do Nothing)
Mode Select-Function Table
Inputs
CP CE
LI
LI
Lh
XH
Dn
h
I
X
X
Output
Qn
H
L
No Change
No Change
TL F 9525 – 3
H e HIGH Voltage Level
h e HIGH Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
L e LOW Voltage Level
I e LOW Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
X e Immaterial
L e LOW-to-HIGH Clock Transition
Logic Diagram
TL F 9525 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F377
Description Octal D Flip-Flop with Clock Enable
Maker National Semiconductor
Total Page 8 Pages
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