DM54LS190 Datasheet, National Semiconductor

Y Counts 8-4-2-1 BCD or binary Y Single down up count control line Y Count enable control input Y Ripple clock output for cascading Y Asynchronously presettable with load.

Y Average propagation delay 20 ns Y Typical clock frequency 25 MHz Y Typical power dissipation 100 mW Connection Diagra.

These circuits are synchronous reversible up down counters The LS191 is a 4-bit binary counter and the LS190 is a BCD counter Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously .