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National Semiconductor Electronic Components Datasheet

PC87413 Datasheet

LPC ServerI/O for Servers and Workstations

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July 2003
Revision 1.2
PC87413, PC87414, PC87416, PC87417
LPC ServerI/O for Servers and Workstations
General Description
The National Semiconductor® PC8741x family of LPC Serv-
erI/O devices (“PC8741x”) comprises highly integrated Ad-
vanced I/O products. The PC8741x is targeted for a wide
range of servers and workstations that use the Low Pin Count
(LPC) bus for the host interface and the serial ACCESS.bus
or SMBus® for the embedded controller interface.
The PC8741x features an X-Bus extension for read and write
operations over the X-Bus for both LPC and ACCESS.bus
cycles. Boot Flash and I/O devices can be accessed over this
X-Bus.
Embedded controllers can access the PC8741x and its X-Bus
via the ACCESS.bus or SMBus serial interface when VSB
exists, regardless of the LPC bus state. Some of the
PC8741x logical devices can be disabled, or their pins can be
floated, under control of the VSB-powered serial bus.
The PC8741x provides a VSB-powered high-frequency clock
for on-chip peripherals and for other VSB-powered platform
components.
The PC8741x’s extended wake-up support complements the
chipset’s ACPI controller and the platform embedded control-
lers. The PC8741x can monitor the Power and Sleep buttons
and control the power supply of simple platforms that lack an
embedded controller. The System Wake-Up Control (SWC)
module is powered by VSB and VBAT power supplies. It sup-
ports flexible wake-up and power-off request mechanisms in
any sleep state. It features Main and Standby power-on
elapsed-time counters.
The PC8741x also incorporates a Floppy Disk Controller
(FDC), two serial ports (UARTs), a Keyboard and Mouse
Controller (KBC), a Real-Time Clock (RTC), a fully compliant
IEEE 1284 Parallel Port, General-Purpose Input/Output
(GPIO) for a total of 51 ports and an Interrupt Serializer for
Parallel IRQs.
Outstanding Features
s LPC Interface, based on Intel’s LPC Interface Specifi-
cation, Revision 1.0, September 29th, 1997
s VSB-powered access to modules through ACCESS.bus
or SMBus (PC87413 and PC87417)
s X-Bus Extension for memory and I/O (PC87416 and
PC87417)
s PC01 Revision 0.5 and ACPI Revision 1.0b compliant
s ServerI/O modules: Parallel Port, FDC, two Serial Ports
(UARTs) and a Keyboard and Mouse Controller (KBC)
s Y2K-compliant RTC with 242 bytes of RAM
s 51 GPIO ports with a variety of wake-up events
s Extremely low current consumption in Battery Backup mode
s 128-pin PQFP package
Block Diagram
PC87417(See page 5 for other PC8741x diagrams.)
Serial
Interface
ServerI/O
Clock
Serial
VDD Port 1
Serial
Interface
Serial
Port 2
Parallel Port
Interface
IEEE 1284
Parallel Port
Floppy Drive Keyboard Mouse LPC Serial
Interface Interface Interface Interface IRQ
Floppy Disk
Controller
Keyboard &
Mouse Controller
LPC Bus
Interface
VBAT
VSB
System
Wake-Up Control
Power
On
Timers
RTC
Internal Clocks
Clock
GPIO
Generator Ports
X-Bus
Extension
Device
Configuration
ACCESS.bus
Interface
Wake-Up Power SCI &
Events Control SMI
Low-F High-F I/O X-Bus XIRQ Clock Serial
32.768 KHz Clock Clock Ports Interface
Data
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other
brand or product names are trademarks or registered trademarks of their respective holders.
© 2003 National Semiconductor Corporation
www.national.com


National Semiconductor Electronic Components Datasheet

PC87413 Datasheet

LPC ServerI/O for Servers and Workstations

No Preview Available !

Features
Bus Interfaces
s LPC Bus Interface
Based on Intel’s LPC Interface Specification Revi-
sion 1.0, September 29, 1997
Synchronous cycles using up to 33 MHz bus clock
8-bit I/O and Memory read and write cycles
Up to four 8-bit DMA channels
Serial IRQ
Supports bootable memory
Reset input
CLKRUN support
FWH Transaction support
s ACCESS.bus (ACB) Interface (PC87413 and PC87417)
Enables a system controller to access the internal
functions and the X-Bus extension
Supports slave operation compatible with:
Intel SMBus
ACCESS.bus
Proprietary commands for read/write byte from/to:
Internal register
X-Bus I/O device
X-Bus memory device
Slave address:
Two values selected by strap
Programmable through the LPC bus
VBAT backed-up
Concurrent access with the LPC bus
VSB powered
Optional internal pull-up on the ACBDAT and
ACBCLK pins
s X-Bus Extension (PC87416 and PC87417)
Supports I/O and Memory read/write operations
8-bit data bus, 28-bit address
Multiplexed address-data lines:
Four direct address lines
Partial non-multiplexed option
Boot configuration selected by straps
Four chip-select outputs, each supporting multiple
zones:
Up to 32 MByte BIOS memory zones
Up to 32 MByte user-defined memory zones
Four user-defined I/O zones
Test port and other I/O ports
Optional indirect addressing of memory
XRD-XEN or XWR-XR/W mode support
Supports both slow and fast devices
Accessible from both LPC and ACB buses
Programmable protection control over access from
the LPC bus
VSB powered
External Interrupt support via XIRQ pin
s Configuration Control (via LPC bus)
Compliant with PC01 Specification Revision 0.5,
November 2, 1999
Plug and Play (PnP) Configuration register structure
Base Address strap to setup the address of the
Index-Data register pair
Flexible resource allocation for all logical devices:
Relocatable base address
15 IRQ routing options to serial IRQ
Up to four optional 8-bit DMA channels
ACCESS.bus control over pin multiplexing, module
disable and output TRI-STATE for all Legacy mod-
ules (PC87413 and PC87417)
Legacy Modules
s Serial Ports 1 and 2
Software compatible with the 16550A and the 16450
Supports shadow register for write-only bit monitoring
UART data rates up to 1.5 Mbaud
s IEEE 1284-compliant Parallel Port
ECP, with Level 2 (14 mA sink and source output
buffers)
Software or hardware control
Enhanced Parallel Port (EPP) compatible with EPP
1.7 and EPP 1.9
Supports EPP as mode 4 of the Extended Control
Register (ECR)
Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
Supports a demand DMA mode mechanism and a
DMA fairness mechanism for improved bus utilization
Protection circuit that prevents damage to the
parallel port when a printer connected to it powers
up or is operated at high voltages, even if the device
is in power-down state
Optional outputs TRI-STATE by external pin
s Floppy Disk Controller (FDC)
Programmable write protect
Supports FM and MFM modes
Supports Enhanced mode command for three-mode
Floppy Disk Drive (FDD)
Perpendicular recording drive support for 2.88 MB
Burst and Non-Burst modes
Full support for IBM Tape Drive Register (TDR) im-
plementation of AT and PS/2 drive types
16-byte FIFO
Error-free handling of data overrun and underrun
conditions during DMA transactions (i.e., does not
lose data or status bytes and is free of the NEC765A
bug)
Software compatible with the PC8477, which
contains a superset of the FDC functions in the
µDP8473, NEC µPD765A/B and N82077
High-performance digital separator
Supports standard 5.25" and 3.5" FDDs
Supports up to four FDDs
www.national.com
2
Revision 1.2


Part Number PC87413
Description LPC ServerI/O for Servers and Workstations
Maker National Semiconductor
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PC87413 Datasheet PDF






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