MC10E150 Datasheet | onsemi

Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low. The 100 Series contains temperature pensation. Features http://onsemi. - 800 ps Max. Propagation Delay - PECL Mode Operating Range: VCC = 4.2 V to 5.7 V - - - - - with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = - 4.2 V to - 5.7 V Internal Input 50 k W Pulldown Resistors ESD Protection: Human Body Model; > 2 k V, Machine Model; > 200 V Charged Device Model; > 2 k V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb- Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V- 0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 173 devices Pb- Free Packages are Available- PLCC- 28 FN SUFFIX CASE 776 MARKING DIAGRAM- MCxxx E150FNG AWLYYWW - - - xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb- Free Package - For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. - For additional information on our Pb- Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor ponents Industries, LLC, 2006 December, 2006 - Rev. 10 Publication Order Number: MC10E150/D MC10E150, MC100E150 MR LEN2 LEN1 NC VCCO 25 D5 D4 D3 VEE D2 D1 D0 26 27 28 Q5 20 Q5 19 18 17 16 Q4 Q4 VCC Q3 Q3 Q2 Q2 D0 Q0 Q0 Q1 R Q1 Q2 R Q2 Q3 R Q3 Q4 R Q4 Q5 R...