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  ON Semiconductor Electronic Components Datasheet  

NB2308A Datasheet

Zero Delay Clock Buffer

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NB2308A
3.3 V Zero Delay
Clock Buffer
The NB2308A is a versatile, 3.3 V zero delay buffer designed to
distribute highspeed clocks. It is available in a 16 pin package. The
part has an onchip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The inputtooutput
propagation delay is guaranteed to be less than 250 ps, and the
outputtooutput skew is guaranteed to be less than 200 ps.
The NB2308A has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
threestated. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2308A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
The NB2308A is available in five different configurations (Refer to
NB2308A Configurations Table). The NB2308Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2308Ax1H is the highdrive version of
the 1 and the rise and fall times on this device are much faster.
The NB2308Ax2 allows the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. The NB2308Ax3
allows the user to obtain 4X and 2X frequencies on the outputs.
The NB2308Ax4 enables the user to obtain 2X clocks on all outputs.
Thus, the part is extremely versatile, and can be used in a variety of
applications.
The NB2308Ax5H is a highdrive version with REF/2 on both
banks.
Features
Zero Input Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations Refer to NB2308A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple LowSkew Outputs
OutputOutput Skew Less than 200 ps
DeviceDevice Skew Less than 700 ps
Two banks of four outputs, threestateable by two select inputs
Less than 200 ps CycletoCycle Jitter
Available in 16pin SOIC and TSSOP Packages
3.3V operation
Advanced 0.35 m CMOS Technology
These are PbFree Devices**
http://onsemi.com
MARKING
DIAGRAMS*
16
1
SOIC16
D SUFFIX
CASE 751B
16
XXXXXXXXXG
AWLYWW
1
16
1
TSSOP16
DT SUFFIX
CASE 948F
16
XXXX
XXXX
ALYWG
G
1
XXXX = Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our PbFree strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 3
1
Publication Order Number:
NB2308A/D


  ON Semiconductor Electronic Components Datasheet  

NB2308A Datasheet

Zero Delay Clock Buffer

No Preview Available !

NB2308A pdf
NB2308A
REF
Extra Divider (5H)
B2
B2
PLL
Extra Divider (3, 4)
MUX
S2
SELECT INPUT
DECODING
S1 B2
Extra Divider (2, 3)
FBK
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
Figure 1. Block Diagram
(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)
CLKB4
Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial)
Device
NB2308Ax1
NB2308Ax1H
NB2308Ax2
NB2308Ax2
NB2308Ax3
NB2308Ax3
NB2308Ax4
NB2308Ax5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference B2
Bank B Frequency
Reference
Reference
Reference B2
Reference
Reference or Reference (Note 1)
2 X Reference
2 X Reference
Reference B2
1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the NB2308Ax2.
Table 2. SELECT INPUT DECODING
S2 S1
Clock A1 A4
Clock B1 B4
00
Threestate
Threestate
01
Driven
Threestate
1 0 Driven (Note 2)
Driven
11
Driven
Driven
2. Outputs inverted on 23082 and 23083 in bypass mode, S2 = 1 and S1 = 0.
Output Source
PLL
PLL
Reference
PLL
PLL ShutDown
Y
N
Y
N
http://onsemi.com
2


Part Number NB2308A
Description Zero Delay Clock Buffer
Maker ON Semiconductor
Total Page 12 Pages
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