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  ON Semiconductor Electronic Components Datasheet  

NB3F8L3005C Datasheet

3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer

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NB3F8L3005C
3.3V / 2.5V / 1.8V / 1.5V
2:1:5 LVCMOS Fanout Buffer
Description
The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOx supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or a differential/SE Clock /
Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, or
SSTL and Single−Ended levels. The MUX control line, SEL selects
CLK/CLK, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (Hi−Z) when Low per
Table 4.
Outputs consist of five single−ended LVCMOS outputs.
www.onsemi.com
QFN24
G SUFFIX
CASE 485DJ
MARKING
DIAGRAM
1
NB3F8L
3005C
ALYWG
G
Features
Five LVCMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, SSTL, or
LVCMOS/LVTTL
Crystal Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 156.25 MHz, (12 kHz – 20 MHz):
0.03 ps (Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V ± 5%
Single 2.5 V ± 5%
Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial Temperature Range: −40°C to 85°C
These are Pb−Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 1
1
Publication Order Number:
NB3F8L3005C/D


  ON Semiconductor Electronic Components Datasheet  

NB3F8L3005C Datasheet

3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer

No Preview Available !

NB3F8L3005C
VDD
GND
SEL
CLK
CLK
BANK A
VDDOA
Q0
Q1
XTAL_IN
XTAL_OUT
OSC
BANK B
VDDOB
Q2
Q3
Q4
OE SYNC
Figure 1. Simplified Logic Diagram
GND 1
VDDOA 2
Q0 3
GND 4
Q1 5
VDDOA 6
24 23 22 21 20 19
Exposed Pad
(EP)
NB3F8L3005C
18 VDDOB
17 Q4
16 GND
15 Q3
14 VDD0B
13 Q2
7 8 9 10 11 12
Figure 2. Pinout Configuration (Top View)
www.onsemi.com
2


Part Number NB3F8L3005C
Description 3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer
Maker ON Semiconductor
Total Page 13 Pages
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