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NB3L8533 Datasheet

2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer

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NB3L8533
2.5V/3.3V Differential 2:1
MUX to 4 LVPECL Fanout
Buffer
Description
The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L8533 features a multiplexed input which can be driven by
either a differential or single−ended input to allow for the distribution
of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential clock inputs, CLK and
CLK, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When CLK_SEL is HIGH, the Differential
PCLK and PCLK inputs are selected.
The common enable (CLK_EN) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
Features
650 MHz Maximum Clock Output Frequency
CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL
PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL
Four Differential LVPECL Clock Outputs
1.5 ns Maximum Propagation Delay
Operating Range: VCC = 2.375 V to 3.630 V
LVCMOS Compatible Control Inputs
Selectable Differential Clock Inputs
Synchronous Clock Enable
30 ps Max. Skew Between Outputs
−40°C to +85°C Ambient Operating Temperature Range
TSSOP−20 Package
These are Pb−Free Devices
Applications
Computing and Telecom
Routers, Servers and Switches
Backplanes
www.onsemi.com
MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
NB3L
8533
ALYW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
+
CLK_EN
D
Q
CLK
CLK
+
PCLK
PCLK
+
CLK_SEL
0
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Simplified Logic Diagram of
NB3L8533
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 1
1
Publication Order Number:
NB3L8533/D


  ON Semiconductor Electronic Components Datasheet  

NB3L8533 Datasheet

2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer

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NB3L8533
VEE
CLK_EN
CLK_SEL
CLK
CLK
PCLK
PCLK
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20 Q0
19 Q0
18 VCC
17 Q1
16 Q1
15 Q2
14 Q2
13 VCC
12 Q3
11 Q3
Figure 2. Pinout Diagram (Top View)
Table 1. FUNCTIONS
Inputs
Outputs
CLK_EN
CLK_SEL
Input Function
Output Function
Qx Qx
0 0 CLK input selected
Disabled
LOW
HIGH
0 1 PCLK Inputs Selected
Disabled
LOW
HIGH
1 0 CLK input selected
Enabled
CLK Invert of CLK
1 1 PCLK Inputs Selected
Enabled
PCLK
Invert of PCLK
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
Table 2. PIN DESCRIPTION
Pin Number
1
Name
VEE
2 CLK_EN
3 CLK_SEL
4 CLK
5 CLK
6 PCLK
7 PCLK
8 NC
9 NC
10 VCC
11 Q3
12 Q3
13 VCC
14 Q2
15 Q2
16 Q1
17 Q1
18 VCC
19 Q0
20 Q0
I/O
Power
LVCMOS/LVTTL
Input
LVCMOS/LVTTL
Input
Input
Input
Input
Input
Power
LVPECL Output
LVPECL Output
Power
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
Power
LVPECL Output
LVPECL Output
Open
Default
Pull-up
Pull-down
Description
Negative (Ground) Power Supply pin must be externally connect-
ed to power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
Clock Input Select (HIGH selects PCLK, LOW selects CLK input)
Pull-down
Pull-up
Pull-down
Pull-up
Non−inverted Differential Clock Input. Float open when unused.
Inverted Differential Clock Input. Float open when unused.
Non−inverted Differential Clock Input. Float open when unused.
Inverted Differential Clock Input. Float open when unused.
No Connect
No Connect
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Output
True Differential Output
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Output
True Differential Output
Complement Differential Output
True Differential Output
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
Complement Differential Output
True Differential Output
www.onsemi.com
2


Part Number NB3L8533
Description 2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer
Maker ON Semiconductor
Total Page 10 Pages
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