2.5V/3.3V Differential 2:1
MUX to 4 LVPECL Fanout
The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L8533 features a multiplexed input which can be driven by
either a differential or single−ended input to allow for the distribution
of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential clock inputs, CLK and
CLK, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When CLK_SEL is HIGH, the Differential
PCLK and PCLK inputs are selected.
The common enable (CLK_EN) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
• 650 MHz Maximum Clock Output Frequency
• CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL
• PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL
• Four Differential LVPECL Clock Outputs
• 1.5 ns Maximum Propagation Delay
• Operating Range: VCC = 2.375 V to 3.630 V
• LVCMOS Compatible Control Inputs
• Selectable Differential Clock Inputs
• Synchronous Clock Enable
• 30 ps Max. Skew Between Outputs
• −40°C to +85°C Ambient Operating Temperature Range
• TSSOP−20 Package
• These are Pb−Free Devices
• Computing and Telecom
• Routers, Servers and Switches
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
Figure 1. Simplified Logic Diagram of
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 1
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