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NB3L83948C Key Features

  • 2.5 V / 3.3V (VDD = VDDO) or
  • 350 MHz Clock Support
  • Accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS
  • LVCMOS patible Control Inputs
  • 12 LVCMOS Clock Outputs
  • Synchronous Clock Select
  • Output Enable to High Z State Control
  • 100 ps Max. Skew Between Outputs
  • Industrial Temp. Range -40°C to +85°C
  • 32-pin LQFP Package

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NB3L83948C Description

The NB3L83948C is a pure 2.5 V / 3.3 V (VDD = VDDO) or mixed mode 3.3 V Core (VDD) / 2.5 V Output (VDDO) clock distribution buffer with the capability to select either a differential LVPECL / LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL patible input clock, such as a Primary or a Test Clock. All other control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS level patible. The NB3L83948C provides an...