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  ON Semiconductor Electronic Components Datasheet  

NB3L8543S Datasheet

2.5V/3.3V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs

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NB3L8543S
2.5 V/3.3 V Differential 2:1
MUX to 4 LVDS Clock
Fanout Buffer Outputs with
Clock Enable and Clock
Select
Description
The NB3L8543S is a high performance, low skew 1to4 LVDS
Clock Fanout Buffer.
The NB3L8543S features a multiplexed input which can be driven
by either a differential or singleended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The CLK_SEL pin will select the differential CLK and CLK inputs
when LOW (or left open and pulled LOW by the internal pulldown
resistor). When CLK_SEL is HIGH, the differential PCLK and PCLK
inputs are selected.
The common clock enable pin, CLK_EN, is synchronous so that the
outputs will only be enabled/disabled when they are already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the outputs during asynchronous assertion/deassertion of the clock
enable pin. The internal flip flop is clocked on the falling edge of the
input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Features
Four Differential LVDS Output Pairs
Two Selectable Differential Clock Inputs
CLK/CLK Can Accept LVPECL, LVDS, HCSL, SSTL and HSTL
PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL
Maximum Output Frequency: 650 MHz
Additive Phase Jitter, RMS: 50 fs (typical)
Output Skew: 40 ps (maximum)
Parttopart Skew: 200 ps (maximum)
Propagation Delay: 1.9 ns (maximum)
Operating Range: VDD = 2.5 V ±5% or 3.3 V ±10%
40°C to +85°C Ambient Operating Temperature Range
TSSOP20 Package
These are PbFree Devices
www.onsemi.com
MARKING
DIAGRAM
TSSOP20
DT SUFFIX
CASE 948E
NB3L
8543
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
+
CLK_EN
CLK
CLK
+
PCLK
PCLK
+
CLK_SEL
D
Q
0
1
+
OE
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2014 Rev. 1
1
Publication Order Number:
NB3L8543E/D


  ON Semiconductor Electronic Components Datasheet  

NB3L8543S Datasheet

2.5V/3.3V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs

No Preview Available !

NB3L8543S
GND
CLK_EN
CLK_SEL
CLK
CLK
PCLK
PCLK
OE
GND
VDD
1
2
3
4
5
6
7
8
9
10
20 Q0
19 Q0
18 VDD
17 Q1
16 Q1
15 Q2
14 Q2
13 GND
12 Q3
11 Q3
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Number
1, 9, 13
Name
GND
I/O
Power
2
CLK_EN
NC
3
CLK_SEL
NC
4 CLK Input
5 CLK Input
6
PCLK
Input
7
PCLK
Input
8 OE NC
10 ,18
VDD
Power
11, 14, 16,
19
12, 15, 17,
20
Q[3:0]
Q[3:0]
Output
Output
Open
Default
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pullup
Description
Negative (Ground) Power Supply pins must be externally connected
to power supply to guarantee proper operation.
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW). See Figure 3.
Clock Input Select (HIGH selects PCLK/PCLK, LOW selects CLK/
CLK input
True Standard Clock Input. Float open when unused.
Invert Standard Clock Inputs. Float open when unused.
True Peripheral Clock Input. Float open when unused.
Invert Peripheral Clock Inputs. Float open when unused.
Output Enable Control. When HIGH, the outputs are active and en-
abled. When LOW, the outputs are high impedance disabled.
Positive Power Supply pin must be externally connected to power
supply to guarantee proper operation.
Invert LVDS Outputs
True LVDS Outputs
www.onsemi.com
2


Part Number NB3L8543S
Description 2.5V/3.3V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs
Maker ON Semiconductor
Total Page 12 Pages
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